soc/intel/skylake: Use common/block/gpio

Other than switch to use common gpio implementation for skylake based
platform, also apply the needed changes for purism board.

Change-Id: I06e06dbcb6d0d6fe277dfad57b82aca51f94b099
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 54 insertions, 295 deletions

diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index 4f809cf480..13a0a7ab62 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -18,184 +18,8 @@
 #define _SOC_GPIO_H_
 
 #include <soc/gpio_defs.h>
-
-#define GPIO_DWx_SIZE(x)	(sizeof(uint32_t) * (x))
+#include <intelblocks/gpio.h> /* intelblocks/gpio.h depends on definitions in
+				soc/gpio_defs.h */
 
 #define CROS_GPIO_DEVICE_NAME	"INT344B:00"
-
-#ifndef __ACPI__
-#include <stdint.h>
-#include <stddef.h>
-
-typedef uint32_t gpio_t;
-
-/* Structure to represent GPI status for GPE and SMI. Use helper
- * functions for interrogating particular GPIs. */
-struct gpi_status {
-	uint32_t grp[GPIO_NUM_GROUPS];
-};
-
-/*
- * Clear GPI SMI status and fill in the structure representing enabled
- * and set status.
- */
-void gpi_clear_get_smi_status(struct gpi_status *sts);
-
-/* Return 1 if gpio is set in the gpi_status struct. Otherwise 0. */
-int gpi_status_get(const struct gpi_status *sts, gpio_t gpi);
-
-/*
- * Set the GPIO groups for the GPE blocks. The gpe0_route is interpreted
- * as the packed configuration for GPE0_DW[2:0]:
- *  dw0 = gpe0_route[3:0]
- *  dw1 = gpe0_route[7:4]
- *  dw2 = gpe0_route[11:8].
- */
-void gpio_route_gpe(uint16_t gpe0_route);
-
-/* Configure the pads according to the pad_config array. */
-struct pad_config;
-void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
-
-#define PAD_FIELD_VAL(field_, val_) \
-	(((val_) & field_ ## _MASK) << field_ ## _SHIFT)
-
-#define PAD_FIELD(field_, setting_) \
-	PAD_FIELD_VAL(field_, field_ ## _ ## setting_)
-
-/*
- * This encodes all the fields found within the dw0 register for each
- * pad. It directly follows the register specification:
- *   rst - reset type when pad configuration is reset
- *   rxst - native function routing: raw buffer or internal buffer
- *   rxraw1 - drive fixed '1' for Rx buffer
- *   rxev - event filtering for pad value: level, edge, drive '0'
- *   rxgf - glitch filter enable
- *   rxinv - invert the internal pad state
- *   gpiioapic - route to IOxAPIC
- *   gpisci -  route for SCI
- *   gpismi - route for SMI
- *   gpinmi - route for NMI
- *   mode -  GPIO vs native function
- *   rxdis - disable Rx buffer
- *   txdis - disable Tx buffer
- */
-#define _DW0_VALS(rst, rxst, rxraw1, rxev, rxgf, rxinv, gpiioapic, gpisci, \
-			gpismi, gpinmi, mode, rxdis, txdis) \
-	(PAD_FIELD(PADRSTCFG, rst) | \
-	 PAD_FIELD(RXPADSTSEL, rxst) | \
-	 PAD_FIELD(RXRAW1, rxraw1) | \
-	 PAD_FIELD(RXEVCFG, rxev) | \
-	 PAD_FIELD(PREGFRXSEL, rxgf) | \
-	 PAD_FIELD(RXINV, rxinv) | \
-	 PAD_FIELD(GPIROUTIOXAPIC, gpiioapic) | \
-	 PAD_FIELD(GPIROUTSCI, gpisci) | \
-	 PAD_FIELD(GPIROUTSMI, gpismi) | \
-	 PAD_FIELD(GPIROUTNMI, gpinmi) | \
-	 PAD_FIELD(PMODE, mode) | \
-	 PAD_FIELD(GPIORXDIS, rxdis) | \
-	 PAD_FIELD(GPIOTXDIS, txdis))
-
-#define _PAD_CFG_ATTRS(pad_, term_, dw0_, attrs_)			\
-	{								\
-		.pad = pad_,						\
-		.attrs = PAD_FIELD(PAD_TERM,  term_) | attrs_,		\
-		.dw0 = dw0_,						\
-	}
-
-/* Default to ACPI owned. Ownership only matters for GPI pads. */
-#define _PAD_CFG(pad_, term_, dw0_) \
-	_PAD_CFG_ATTRS(pad_, term_, dw0_, PAD_FIELD(HOSTSW, ACPI))
-
-/* Native Function - No Rx buffer manipulation */
-#define PAD_CFG_NF(pad_, term_, rst_, func_) \
-	_PAD_CFG(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO))
-
-/* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. */
-#define PAD_CFG_NF_1V8(pad_, term_, rst_, func_) \
-	_PAD_CFG_ATTRS(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, \
-		NO, NO, NO, NO, func_, NO, NO), PAD_FIELD(PAD_TOL, 1V8))
-
-/* Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
-   GPIO TX/RX will be disabled. */
-#define PAD_CFG_NC(pad_) \
-	_PAD_CFG(pad_, NONE, \
-	_DW0_VALS(DEEP, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, YES))
-
-/* General purpose output with termination. */
-#define PAD_CFG_TERM_GPO(pad_, val_, term_, rst_) \
-	_PAD_CFG(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, NO) \
-		| PAD_FIELD_VAL(GPIOTXSTATE, val_))
-
-/* General purpose output. By default no termination. */
-#define PAD_CFG_GPO(pad_, val_, rst_) \
-	PAD_CFG_TERM_GPO(pad_, val_, NONE, rst_)
-
-/* General purpose input with no special IRQ routing. */
-#define PAD_CFG_GPI(pad_, term_, rst_) \
-	_PAD_CFG_ATTRS(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\
-	PAD_FIELD(HOSTSW, GPIO))
-
-/* General purpose input passed through to GPIO interrupt */
-#define PAD_CFG_GPI_INT(pad_, term_, rst_, trig_) \
-	_PAD_CFG_ATTRS(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, trig_, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\
-	PAD_FIELD(HOSTSW, GPIO))
-
-/* General purpose input passed through to IOxAPIC. Assume APIC logic can
- * handle polarity/edge/level constraints. */
-#define PAD_CFG_GPI_APIC(pad_, term_, rst_) \
-	_PAD_CFG(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, GPIO, NO, YES))
-
-/* General purpose input passed through to IOxAPIC as inverted input. */
-#define PAD_CFG_GPI_APIC_INVERT(pad_, term_, rst_) \
-	_PAD_CFG(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, YES, YES, NO, NO, NO, GPIO, NO, \
-		  YES))
-
-/* General purpose input passed through to IOxAPIC. This assumes edge
- * triggered events. */
-#define PAD_CFG_GPI_APIC_EDGE(pad_, term_, rst_) \
-	_PAD_CFG(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, EDGE, NO, NO, YES, NO, NO, NO, GPIO, NO, YES))
-
-/* General purpose input routed to SCI. This assumes edge triggered events. */
-#define PAD_CFG_GPI_ACPI_SCI(pad_, term_, rst_, inv_) \
-	_PAD_CFG_ATTRS(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, EDGE, NO, inv_, \
-		NO, YES, NO, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI))
-
-#define PAD_CFG_GPI_ACPI_SCI_LEVEL(pad_, term_, rst_, inv_) \
-	_PAD_CFG_ATTRS(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, inv_, \
-		NO, YES, NO, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI))
-
-/* General purpose input routed to SMI. This assumes edge triggered events. */
-#define PAD_CFG_GPI_ACPI_SMI(pad_, term_, rst_, inv_) \
-	_PAD_CFG_ATTRS(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, EDGE, NO, inv_, \
-		NO, NO, YES, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI))
-
-/*
- * The 'attrs' field carries the termination in bits 13:10 and tolerance in bit
- * 25 to match up with thd DW1 pad configuration register. Additionally, other
- * attributes can be applied such as the ones below. Bit allocation matters.
- */
-#define HOSTSW_SHIFT		0
-#define HOSTSW_MASK		1
-#define HOSTSW_ACPI		HOSTSW_OWN_ACPI
-#define HOSTSW_GPIO		HOSTSW_OWN_GPIO
-
-struct pad_config {
-	uint16_t pad;
-	uint32_t attrs;
-	uint32_t dw0;
-};
-
-#endif /* __ACPI__ */
 #endif
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h
index 34461f2061..137b37e613 100644
--- a/src/soc/intel/skylake/include/soc/gpio_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_defs.h
@@ -15,13 +15,31 @@
 
 #ifndef _SOC_GPIO_DEFS_H_
 #define _SOC_GPIO_DEFS_H_
-
+#ifndef __ACPI__
+#include <stddef.h>
+#endif
 #if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
 # include <soc/gpio_pch_h_defs.h>
 #else
 # include <soc/gpio_soc_defs.h>
 #endif
 
+#define GPIO_NUM_PAD_CFG_REGS   2 /* DW0, DW1 */
+
+#define NUM_GPIO_COMx_GPI_REGS(n)	\
+	(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
+#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
+#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
+#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
+
+#define NUM_GPI_STATUS_REGS	\
+		((NUM_GPIO_COM0_GPI_REGS) +\
+		(NUM_GPIO_COM1_GPI_REGS) +\
+		(NUM_GPIO_COM3_GPI_REGS) +\
+		(NUM_GPIO_COM2_GPI_REGS))
+
 /*
  * IOxAPIC IRQs for the GPIOs
  */
@@ -76,6 +94,7 @@
 #define GPP_B21_IRQ		0x45
 #define GPP_B22_IRQ		0x46
 #define GPP_B23_IRQ		0x47
+
 /* Group C */
 #define GPP_C0_IRQ		0x48
 #define GPP_C1_IRQ		0x49
@@ -200,121 +219,13 @@
 #define GPD11_IRQ		0x5b
 
 /* Register defines. */
-#define MISCCFG_OFFSET		0x10
-#define  GPIO_DRIVER_IRQ_ROUTE_MASK	8
-#define  GPIO_DRIVER_IRQ_ROUTE_IRQ14	0
-#define  GPIO_DRIVER_IRQ_ROUTE_IRQ15	8
-#define  GPE_DW_SHIFT		8
-#define  GPE_DW_MASK		0xfff00
-#define PAD_OWN_REG_OFFSET	0x20
-#define  PAD_OWN_PADS_PER	8
-#define  PAD_OWN_WIDTH_PER	4
-#define  PAD_OWN_MASK		0x03
-#define  PAD_OWN_HOST		0x00
-#define  PAD_OWN_ME		0x01
-#define  PAD_OWN_ISH		0x02
-#define HOSTSW_OWN_REG_OFFSET	0xd0
-#define  HOSTSW_OWN_PADS_PER	24
-#define  HOSTSW_OWN_ACPI	0
-#define  HOSTSW_OWN_GPIO	1
-#define PAD_CFG_DW_OFFSET	0x400
-	/* PADRSTCFG - when to reset the pad config */
-#define  PADRSTCFG_SHIFT	30
-#define  PADRSTCFG_MASK		0x3
-#define  PADRSTCFG_DSW_PWROK	0
-#define  PADRSTCFG_DEEP		1
-#define  PADRSTCFG_PLTRST	2
-#define  PADRSTCFG_RSMRST	3
-	/* RXPADSTSEL - raw signal or internal state */
-#define  RXPADSTSEL_SHIFT	29
-#define  RXPADSTSEL_MASK	0x1
-#define  RXPADSTSEL_RAW		0
-#define  RXPADSTSEL_INTERNAL	1
-	/* RXRAW1 - drive 1 instead instead of pad value */
-#define  RXRAW1_SHIFT		28
-#define  RXRAW1_MASK		0x1
-#define  RXRAW1_NO		0
-#define  RXRAW1_YES		1
-	/* RXEVCFG - Interrupt and wake types */
-#define  RXEVCFG_SHIFT		25
-#define  RXEVCFG_MASK		0x3
-#define  RXEVCFG_LEVEL		0
-#define  RXEVCFG_EDGE		1
-#define  RXEVCFG_DRIVE0		2
-	/* PREGFRXSEL - use filtering on Rx pad */
-#define  PREGFRXSEL_SHIFT	24
-#define  PREGFRXSEL_MASK	0x1
-#define  PREGFRXSEL_NO		0
-#define  PREGFRXSEL_YES		1
-	/* RXINV - invert signal to SMI, SCI, NMI, or IRQ routing. */
-#define  RXINV_SHIFT		23
-#define  RXINV_MASK		0x1
-#define  RXINV_NO		0
-#define  RXINV_YES		1
-	/* GPIROUTIOXAPIC - route to io-xapic or not */
-#define  GPIROUTIOXAPIC_SHIFT	20
-#define  GPIROUTIOXAPIC_MASK	0x1
-#define  GPIROUTIOXAPIC_NO	0
-#define  GPIROUTIOXAPIC_YES	1
-	/* GPIROUTSCI - route to SCI */
-#define  GPIROUTSCI_SHIFT	19
-#define  GPIROUTSCI_MASK	0x1
-#define  GPIROUTSCI_NO		0
-#define  GPIROUTSCI_YES		1
-	/* GPIROUTSMI - route to SMI */
-#define  GPIROUTSMI_SHIFT	18
-#define  GPIROUTSMI_MASK	0x1
-#define  GPIROUTSMI_NO		0
-#define  GPIROUTSMI_YES		1
-	/* GPIROUTNMI - route to NMI */
-#define  GPIROUTNMI_SHIFT	17
-#define  GPIROUTNMI_MASK	0x1
-#define  GPIROUTNMI_NO		0
-#define  GPIROUTNMI_YES		1
-	/* PMODE - mode of pad */
-#define  PMODE_SHIFT		10
-#define  PMODE_MASK		0x3
-#define  PMODE_GPIO		0
-#define  PMODE_NF1		1
-#define  PMODE_NF2		2
-#define  PMODE_NF3		3
-	/* GPIORXDIS - Disable Rx */
-#define  GPIORXDIS_SHIFT	9
-#define  GPIORXDIS_MASK		0x1
-#define  GPIORXDIS_NO		0
-#define  GPIORXDIS_YES		1
-	/* GPIOTXDIS - Disable Tx */
-#define  GPIOTXDIS_SHIFT	8
-#define  GPIOTXDIS_MASK		0x1
-#define  GPIOTXDIS_NO		0
-#define  GPIOTXDIS_YES		1
-	/* GPIORXSTATE - Internal state after glitch filter */
-#define  GPIORXSTATE_SHIFT	1
-#define  GPIORXSTATE_MASK	0x1
-	/* GPIOTXSTATE - Drive value onto pad */
-#define  GPIOTXSTATE_SHIFT	0
-#define  GPIOTXSTATE_MASK	0x1
-	/* TERM - termination control */
-#define  PAD_TERM_SHIFT		10
-#define  PAD_TERM_MASK		0xf
-#define  PAD_TERM_NONE		0
-#define  PAD_TERM_5K_PD		2
-#define  PAD_TERM_20K_PD	4
-#define  PAD_TERM_1K_PU		9
-#define  PAD_TERM_2K_PU		11
-#define  PAD_TERM_5K_PU		10
-#define  PAD_TERM_20K_PU	12
-#define  PAD_TERM_667_PU	13
-#define  PAD_TERM_NATIVE	15
-	/* TOL - voltage tolerance */
-#define  PAD_TOL_SHIFT		25
-#define  PAD_TOL_MASK		0x1
-#define  PAD_TOL_3V3		0	/* 3.3V default */
-#define  PAD_TOL_1V8		1	/* 1.8V tolerant */
-
-#define GPI_GPE_STS_OFFSET	0x140
-#define GPI_GPE_EN_OFFSET	0x160
-#define GPI_SMI_STS_OFFSET	0x180
-#define GPI_SMI_EN_OFFSET	0x1a0
+#define GPIO_MISCCFG		0x10
+#define  GPIO_DRIVER_IRQ_ROUTE_MASK    8
+#define  GPIO_DRIVER_IRQ_ROUTE_IRQ14   0
+#define  GPIO_DRIVER_IRQ_ROUTE_IRQ15   8
+#define HOSTSW_OWN_REG_0	0xd0
+#define PAD_CFG_BASE		0x400
+#define GPI_SMI_STS_0		0x180
+#define GPI_SMI_EN_0		0x1a0
 
 #endif /* _SOC_GPIO_DEFS_H_ */
diff --git a/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h b/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h
index e1be6f0641..c6a23db0a7 100644
--- a/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h
@@ -90,6 +90,9 @@
 #define GPP_B21			45
 #define GPP_B22			46
 #define GPP_B23			47
+
+#define NUM_GPIO_COM0_PADS	(GPP_B23 - GPP_A0 + 1)
+
 /* Group C */
 #define GPP_C0			48
 #define GPP_C1			49
@@ -229,6 +232,9 @@
 #define GPP_H21			178
 #define GPP_H22			179
 #define GPP_H23			180
+
+#define NUM_GPIO_COM1_PADS	(GPP_H23 - GPP_C0 + 1)
+
 /* Group I */
 #define GPP_I0			181
 #define GPP_I1			182
@@ -241,6 +247,9 @@
 #define GPP_I8			189
 #define GPP_I9			190
 #define GPP_I10			191
+
+#define NUM_GPIO_COM3_PADS	(GPP_I10 - GPP_I0 + 1)
+
 /* Group GPD  */
 #define GPD0			192
 #define GPD1			193
@@ -254,4 +263,7 @@
 #define GPD9			201
 #define GPD10			202
 #define GPD11			203
+
+#define NUM_GPIO_COM2_PADS	(GPD11 - GPD0 + 1)
+
 #endif /* _SOC_GPIO_PCH_H_DEFS_H_ */
diff --git a/src/soc/intel/skylake/include/soc/gpio_soc_defs.h b/src/soc/intel/skylake/include/soc/gpio_soc_defs.h
index 9ed61c7fa3..f5633e4ec6 100644
--- a/src/soc/intel/skylake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_soc_defs.h
@@ -88,6 +88,9 @@
 #define GPP_B21			45
 #define GPP_B22			46
 #define GPP_B23			47
+
+#define NUM_GPIO_COM0_PADS	(GPP_B23 - GPP_A0 + 1)
+
 /* Group C */
 #define GPP_C0			48
 #define GPP_C1			49
@@ -163,6 +166,9 @@
 #define GPP_E21			117
 #define GPP_E22			118
 #define GPP_E23			119
+
+#define NUM_GPIO_COM1_PADS	(GPP_E23 - GPP_C0 + 1)
+
 /* Group F */
 #define GPP_F0			120
 #define GPP_F1			121
@@ -197,6 +203,9 @@
 #define GPP_G5			149
 #define GPP_G6			150
 #define GPP_G7			151
+
+#define NUM_GPIO_COM3_PADS	(GPP_G7 - GPP_F0 + 1)
+
 /* Group GPD  */
 #define GPD0			152
 #define GPD1			153
@@ -211,4 +220,7 @@
 #define GPD10			162
 #define GPD11			163
 
+#define NUM_GPIO_COM2_PADS	(GPD11 - GPD0 + 1)
+
+
 #endif /* _SOC_GPIO_SOC_DEFS_H_ */