diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-08-27 14:30:22 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-08 11:30:11 +0000 |
| commit | 11f356c3904321838d69e31f6de3a7fad9d8f42d (patch) | |
| tree | d150b51f9cd7f3de85a1bca320e5a2117519cf87 /src/soc/intel/skylake/include | |
| parent | ce03aaf08c98ce8bc4cb679418f0b82ca50c9a94 (diff) | |
skylake: refactor flash_controller code
There's no need to add any typedefs nor guard code with
ENV_ROMSTAGE. The linker will garbage collect unused functions.
Additionally there were a few errors in the code including
the operation mask wasn't wide enough to clear out old operations
as well as component size decoding was incorrect.
The big difference in the code flow is that the operation
setup is now in one place. The stopwatch API is also used in
order to not open code time calculations.
BUG=chrome-os-partner:42115
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted. Suspended and resumed. event log is populated
for all.
Change-Id: I0ddd42f0744cf8f88da832d7d715663238209a71
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9893fe309104c05edfb158afda6bb029801c0489
Original-Change-Id: I6468f5b9b4a73885b69ebd916861dd2e8e3746b6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295980
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11543
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/flash_controller.h | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h index 25cbce9d1f..91693e3505 100644 --- a/src/soc/intel/skylake/include/soc/flash_controller.h +++ b/src/soc/intel/skylake/include/soc/flash_controller.h @@ -121,22 +121,31 @@ static void writel_(u32 b, void *addr) pci_write_config32(dev, reg, val) #endif /* ENV_SMM */ -#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_MASK (0xf << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_RD (0x0 << HSFC_FCYCLE_SHIFT) #define HSFC_FCYCLE_WR (0x2 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_4KE (0x3 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_64KE (0x4 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_SFDP (0x5 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_JEDECID (0x6 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_WS (0x7 << HSFC_FCYCLE_SHIFT) #define HSFC_FCYCLE_RS (0x8 << HSFC_FCYCLE_SHIFT) -#define HSFC_FDBC (0x3f << HSFC_FDBC_SHIFT) +#define HSFC_FDBC_MASK (0x3f << HSFC_FDBC_SHIFT) #define SPI_READ_STATUS_LENGTH 1 /* Read Status Register 1 */ #define WPSR_MASK_SRP0_BIT 0x80 +#define SPI_FDATA_REGS 16 +#define SPI_FDATA_BYTES (SPI_FDATA_REGS * sizeof(uint32_t)) + typedef struct pch_spi_regs { uint32_t bfpr; uint16_t hsfs; uint16_t hsfc; uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; + uint32_t dlock; + uint32_t fdata[SPI_FDATA_REGS]; uint32_t frap; uint32_t freg[6]; uint32_t _reserved1[6]; |