soc/intel/skylake: drop support for FSP 1.1

This drops support for FSP 1.1 in soc/intel/skylake, after all boards
have been migrated to FSP 2.0, which is backwards compatible.

Any moving of files happens in a follow-up commit to make review easier.

Change-Id: I0dd2eab0edfda0545ff94c3908b8574d5ad830bd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35813
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 0 insertions, 108 deletions

diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
deleted file mode 100644
index 2071d58b49..0000000000
--- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_RAMSTAGE_H_
-#define _SOC_RAMSTAGE_H_
-
-#include <device/device.h>
-#include <fsp/ramstage.h>
-#include <fsp/soc_binding.h>
-
-#include "../../../chip.h"
-
-#define FSP_SIL_UPD SILICON_INIT_UPD
-#define FSP_MEM_UPD MEMORY_INIT_UPD
-
-void soc_irq_settings(FSP_SIL_UPD *params);
-void soc_init_pre_device(void *chip_info);
-void soc_fsp_load(void);
-const char *soc_acpi_name(const struct device *dev);
-
-/* Get igd framebuffer bar */
-uintptr_t fsp_soc_get_igd_bar(void);
-
-#endif
diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
deleted file mode 100644
index 386931043d..0000000000
--- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_ROMSTAGE_H_
-#define _SOC_ROMSTAGE_H_
-
-#include <fsp/romstage.h>
-
-void systemagent_early_init(void);
-void intel_early_me_status(void);
-void enable_smbus(void);
-int smbus_read_byte(unsigned int device, unsigned int address);
-
-#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h
index 74328b217e..a40f439936 100644
--- a/src/soc/intel/skylake/include/soc/bootblock.h
+++ b/src/soc/intel/skylake/include/soc/bootblock.h
@@ -18,12 +18,6 @@
 
 #include <intelblocks/systemagent.h>
 
-#if CONFIG(PLATFORM_USES_FSP1_1)
-#include <fsp/bootblock.h>
-#else
-static inline void bootblock_fsp_temp_ram_init(void) {}
-#endif
-
 /* Bootblock pre console init programming */
 void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 615edac097..18b0c15d64 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -169,14 +169,6 @@ struct chipset_power_state {
 	uint32_t prev_sleep_state;
 } __packed;
 
-/*
- * This is used only in FSP1_1 as we wanted to keep the flow unchanged.
- * Internally fill_power_state calls the new pmc_fill_power_state now
- */
-#if CONFIG(PLATFORM_USES_FSP1_1)
-struct chipset_power_state *fill_power_state(void);
-#endif
-
 /* Return the selected ACPI SCI IRQ */
 int acpi_sci_irq(void);
 
diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h
index de5428a905..5bd649cefc 100644
--- a/src/soc/intel/skylake/include/soc/vr_config.h
+++ b/src/soc/intel/skylake/include/soc/vr_config.h
@@ -19,11 +19,7 @@
 #ifndef _SOC_VR_CONFIG_H_
 #define _SOC_VR_CONFIG_H_
 
-#if CONFIG(PLATFORM_USES_FSP1_1)
-#include <fsp/soc_binding.h>
-#else
 #include <fsp/api.h>
-#endif
 
 struct vr_config {
 
@@ -70,30 +66,6 @@ struct vr_config {
 #define VR_CFG_AMP(i) ((i) * 4)
 #define VR_CFG_MOHMS(i) (uint16_t)((i) * 100)
 
-#if CONFIG(PLATFORM_USES_FSP1_1)
-/* VrConfig Settings for 5 domains
- * 0 = System Agent, 1 = IA Core, 2 = Ring,
- * 3 = GT unsliced,  4 = GT sliced
- */
-enum vr_domain {
-	VR_SYSTEM_AGENT,
-	VR_IA_CORE,
-	VR_RING,
-	VR_GT_UNSLICED,
-	VR_GT_SLICED,
-	NUM_VR_DOMAINS
-};
-
-#define VR_CFG_ALL_DOMAINS_ICC(sa, ia, gt_unsl, gt_sl)	\
-	{							\
-		[VR_SYSTEM_AGENT] = VR_CFG_AMP(sa),		\
-		[VR_IA_CORE]      = VR_CFG_AMP(ia),		\
-		[VR_RING]         = VR_CFG_AMP(0),		\
-		[VR_GT_UNSLICED]  = VR_CFG_AMP(gt_unsl),	\
-		[VR_GT_SLICED]    = VR_CFG_AMP(gt_sl),		\
-	}
-
-#else
 /* VrConfig Settings for 4 domains
  * 0 = System Agent, 1 = IA Core,
  * 2 = GT unsliced,  3 = GT sliced
@@ -114,8 +86,6 @@ enum vr_domain {
 		[VR_GT_SLICED]    = VR_CFG_AMP(gt_sl),		\
 	}
 
-#endif
-
 #define VR_CFG_ALL_DOMAINS_LOADLINE(sa, ia, gt_unsl, gt_sl)	\
 	{							\
 		[VR_SYSTEM_AGENT] = VR_CFG_MOHMS(sa),		\