diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-03-31 14:02:47 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-04-06 00:45:36 +0200 |
| commit | 05a6f29d32c246569b7a0561d35ccbf49eec1fb8 (patch) | |
| tree | a0347e4edb13a2f3bebcbbf8745a4af0a5f18969 /src/soc/intel/skylake/include | |
| parent | 108f87262bf47ce3549fa0c5ed16a40fe916656f (diff) | |
soc/intel/skylake: Add support for GSPI controller
Sky Lake PCH contains two GSPI controllers. Using the common GSPI
controller driver implementation for Intel PCH, add support for GSPI
controller buses on Sky Lake/Kaby Lake.
BUG=b:35583330
Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/iomap.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pci_devs.h | 10 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index a6f7287f3a..e2662cc7c0 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -53,6 +53,7 @@ #define PCH_PWRM_BASE_SIZE 0x10000 #define SPI_BASE_ADDRESS 0xfe010000 +#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 #define GPIO_BASE_SIZE 0x10000 diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 469d7e9992..13114f1f95 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -186,4 +186,14 @@ static inline int spi_devfn_to_bus(unsigned int devfn) return -1; } +static inline int spi_bus_to_devfn(unsigned int bus) +{ + switch (bus) { + case 0: return PCH_DEVFN_SPI; + case 1: return PCH_DEVFN_GSPI0; + case 2: return PCH_DEVFN_GSPI1; + } + return -1; +} + #endif |