diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-03-25 20:01:47 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-03-27 04:23:12 +0000 |
| commit | 2ccc0a4d9fc91a57e1dec8913e6d999402e927a2 (patch) | |
| tree | ef7fd8df9392e99315651d5d45dcf9f975ef3c39 /src/soc/intel/skylake/include/soc/gpio.h | |
| parent | 299ee183c49d22cc90b4289789d8bb6d66145b97 (diff) | |
soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h
Lists of changes:
1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS
2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to
soc/gpio.h. Refer to detailed description below to understand the
motivation behind this change.
An advanced GPIO PM capabilities has been introduced since CNP PCH,
refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions.
Now with TGP PCH, additional bits are defined in the MISCCFG register
for GPIO PM control. This results in different SoCs supporting
different number of bits. The bits defined in earlier platforms
(CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the
common GPIO code to keep the bit definitions in intelblock/gpio.h, but
the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so
that each SoC can provide this as per hardware support.
TEST=On ADL, TGL and JSL platform.
Without this CL :
GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable)
With this CL :
GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable)
Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include/soc/gpio.h')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/gpio.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 283df83b11..b55dea8197 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -8,4 +8,11 @@ soc/gpio_defs.h */ #define CROS_GPIO_DEVICE_NAME "INT344B:00" + +/* + * SPT PCH doesn't support dynamic GPIO PM hence GPIO community + * MISCCFG register doesn't have PM bits + */ +#define MISCCFG_GPIO_PM_CONFIG_BITS 0 + #endif |