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authorNaresh G Solanki <naresh.solanki@intel.com>2016-08-30 20:47:13 +0530
committerMartin Roth <martinroth@google.com>2016-09-19 21:32:22 +0200
commita2d4062d427d18127707306dada5e79d69bd3691 (patch)
treebcf9f53b1f1d74c9d04df6d42af2602ff97038b4 /src/soc/intel/skylake/include/fsp20
parent21130c6508161ada1d28c90a4003c89afc3fd162 (diff)
soc/intel/skylake: Add FSP 2.0 support in ramstage
Add FSP 2.0 support in ramstage. Populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for pre OS screens. Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16592 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include/fsp20')
-rw-r--r--src/soc/intel/skylake/include/fsp20/soc/ramstage.h9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
index 3a9d96bbdd..0ae87f48a5 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
@@ -19,19 +19,18 @@
#include <chip.h>
#include <device/device.h>
-
#include <fsp/api.h>
#include <fsp/util.h>
#include <soc/intel/common/opregion.h>
-#define FSP_SIL_UPD struct FSP_S_CONFIG
-#define FSP_MEM_UPD struct FSP_M_CONFIG
+#define FSP_SIL_UPD FSP_S_CONFIG
+#define FSP_MEM_UPD FSP_M_CONFIG
-void intel_silicon_init(void);
-void mainboard_silicon_init_params(struct FSP_S_CONFIG *params);
+void mainboard_silicon_init_params(FSP_S_CONFIG *params);
void pch_enable_dev(device_t dev);
void soc_init_pre_device(void *chip_info);
void soc_init_cpus(device_t dev);
+void soc_irq_settings(FSP_SIL_UPD *params);
const char *soc_acpi_name(struct device *dev);
extern struct pci_operations soc_pci_ops;