diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-08 00:30:38 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-10-26 15:47:34 +0000 |
| commit | 7ef19036fbfeaad63ccb4dde26b3133d6128d0b8 (patch) | |
| tree | aadb0535e72c94dfc5f359abc37d06acb3c91298 /src/soc/intel/skylake/include/fsp20 | |
| parent | fa62e01b902c00144847103113902c3c817c2443 (diff) | |
soc/intel/skylake: move/rename files after drop of FSP 1.1
Follow-up commit where only files are moved and paths adapted to make
review of the previous commit easier.
Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35868
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/include/fsp20')
| -rw-r--r-- | src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 35 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/fsp20/soc/romstage.h | 32 |
2 files changed, 0 insertions, 67 deletions
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h deleted file mode 100644 index e5660a6f66..0000000000 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_RAMSTAGE_H_ -#define _SOC_RAMSTAGE_H_ - -#include <device/device.h> -#include <fsp/api.h> -#include <fsp/util.h> - -#include "../../../chip.h" - -#define FSP_SIL_UPD FSP_S_CONFIG -#define FSP_MEM_UPD FSP_M_CONFIG - -void mainboard_silicon_init_params(FSP_S_CONFIG *params); -void soc_fsp_load(void); -void soc_init_pre_device(void *chip_info); -void soc_irq_settings(FSP_SIL_UPD *params); -const char *soc_acpi_name(const struct device *dev); - -#endif diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h deleted file mode 100644 index 364bf52529..0000000000 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_ROMSTAGE_H_ -#define _SOC_ROMSTAGE_H_ - -#include <fsp/api.h> - -void mainboard_memory_init_params(FSPM_UPD *mupd); -void systemagent_early_init(void); -int smbus_read_byte(unsigned int device, unsigned int address); -/* Board type */ -enum board_type { - BOARD_TYPE_MOBILE = 0, - BOARD_TYPE_DESKTOP = 1, - BOARD_TYPE_ULT_ULX = 5, - BOARD_TYPE_SERVER = 7 -}; -#endif /* _SOC_ROMSTAGE_H_ */ |