diff options
| author | Naresh G Solanki <naresh.solanki@intel.com> | 2016-08-30 20:47:13 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-19 21:32:22 +0200 |
| commit | a2d4062d427d18127707306dada5e79d69bd3691 (patch) | |
| tree | bcf9f53b1f1d74c9d04df6d42af2602ff97038b4 /src/soc/intel/skylake/include/fsp11 | |
| parent | 21130c6508161ada1d28c90a4003c89afc3fd162 (diff) | |
soc/intel/skylake: Add FSP 2.0 support in ramstage
Add FSP 2.0 support in ramstage.
Populate required Fsp Silicon Init params and configure mainboard
specific GPIOs.
Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for
pre OS screens.
Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16592
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include/fsp11')
| -rw-r--r-- | src/soc/intel/skylake/include/fsp11/soc/ramstage.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h index e469554ba2..8df7796cf7 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h @@ -26,6 +26,7 @@ #define FSP_SIL_UPD SILICON_INIT_UPD #define FSP_MEM_UPD MEMORY_INIT_UPD +void soc_irq_settings(FSP_SIL_UPD *params); void pch_enable_dev(device_t dev); void soc_init_pre_device(void *chip_info); void soc_init_cpus(device_t dev); @@ -33,4 +34,7 @@ const char *soc_acpi_name(struct device *dev); int init_igd_opregion(igd_opregion_t *igd_opregion); extern struct pci_operations soc_pci_ops; +/* Get igd framebuffer bar */ +uintptr_t fsp_soc_get_igd_bar(void); + #endif |