skylake: provide GPE0 routing devicetree configuration

On skylake the GPE0 routing can be dynamically changed to
a particular GPIO group. Provide the ability for the mainboard
to set the route accordingly. If any of the values in the
devicetree are the same the current setting in the PMC register
is used. The GPIO communities need to have matching configuration
for the plumbing to work properly.

BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados w/ and w/o devicetree changes. Fields
     are set accordingly.

Original-Change-Id: I263d648c8ea8a70b21570f01b333d05a5fa2a4e3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291930
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I966d38bc197dbb52a2ba50927c06e243e169afbe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11203
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 23 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 28ed07ebd3..18638873f7 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -71,6 +71,29 @@ static const struct gpio_community *gpio_get_community(gpio_t pad)
 	return NULL;
 }
 
+void gpio_route_gpe(uint16_t gpe0_route)
+{
+	int i;
+	uint32_t misc_cfg;
+	const uint32_t misc_cfg_reg_mask = GPE_DW_MASK;
+
+	misc_cfg = (uint32_t)gpe0_route << GPE_DW_SHIFT;
+	misc_cfg &= misc_cfg_reg_mask;
+
+	for (i = 0; i < ARRAY_SIZE(communities); i++) {
+		uint8_t *regs;
+		uint32_t reg;
+		const struct gpio_community *comm = &communities[i];
+
+		regs = pcr_port_regs(comm->port_id);
+
+		reg = read32(regs + MISCCFG_OFFSET);
+		reg &= ~misc_cfg_reg_mask;
+		reg |= misc_cfg;
+		write32(regs + MISCCFG_OFFSET, reg);
+	}
+}
+
 static void *gpio_dw_regs(gpio_t pad)
 {
 	const struct gpio_community *comm;