diff options
| author | Dhaval Sharma <dhaval.v.sharma@intel.com> | 2016-01-18 17:28:20 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-02-04 17:30:11 +0100 |
| commit | 9dca83c76220172ec7959f9c0b93ad415808d449 (patch) | |
| tree | b463b8cf8351c00ea1355aa225e98157a6aef68a /src/soc/intel/skylake/finalize.c | |
| parent | e2cea4f4582dad7f202a3f6d4fc884b01ec1d52d (diff) | |
intel/skylake: Display ME firmware status before os boot
Display ME firmware status before os boot. Specifically this
patch reads out the ME hfsts1 and hfsts2 status registers that provide
information about overall ME health before device gets disabled.
This change reused most of the code from bdw me_status implementation.
BUG=chrome-os-partner:47384
BRANCH=glados
TEST=Builds and Boots on FAB4 SKU2/3. Can observe me status table
Change-Id: Ia511c4f336d33a6f3b49a344bfbaea6ed227ffeb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a9d0fb411c3921654f0fdcea2a3d4ee601987af2
Original-Change-Id: Ied7e2dcd9a1298a38dfe1eda9296b9ca8eccf6b1
Original-Credits-to: Duncan Laurie <dlaurie@chromium.org>
Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/323260
Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13573
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/finalize.c')
| -rw-r--r-- | src/soc/intel/skylake/finalize.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 8069b405e8..13df7ccdaf 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -24,6 +24,7 @@ #include <spi-generic.h> #include <stdlib.h> #include <soc/lpc.h> +#include <soc/me.h> #include <soc/pci_devs.h> #include <soc/pcr.h> #include <soc/pm.h> @@ -120,6 +121,9 @@ static void pch_finalize_script(void) pmsyncreg |= PMSYNC_LOCK; write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); + /* Display me status before we hide it */ + intel_me_status(); + /* we should disable Heci1 based on the devicetree policy */ config = dev->chip_info; if (config->HeciEnabled == 0) |