diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-10-22 17:11:22 +0200 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-14 08:25:10 +0000 |
| commit | 77509be2c8c3196075669a300954fda5a1ff28c2 (patch) | |
| tree | b1820e9bcdc528fc46300ae6eba794df589034aa /src/soc/intel/skylake/chipset.cb | |
| parent | cfe526dce2b76cce3b4d1009bad676e2ec21afab (diff) | |
soc/intel/xeon_sp: Configure DPR on all stacks
Configure DPR to span the region between cbmem_top and TSEG base.
This region was already unavailable to the OS.
Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/skylake/chipset.cb')
0 files changed, 0 insertions, 0 deletions