diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2017-02-06 21:48:48 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-22 17:42:18 +0100 |
| commit | 63755128961089deba77413dad1f4f6d349a68f5 (patch) | |
| tree | 37fb876dc738b9900ca4bc3a06a89dcfa8d3b5e0 /src/soc/intel/skylake/chip.h | |
| parent | 8e1c12f12e3fb01d2228cca29de188507b3f2cc7 (diff) | |
soc/intel/skylake: Add configs for enabling DCI and TraceHub
Add configs for enabling Intel TraceHub and DCI for aid in debugging.
Change-Id: Ic40f9499c0125070049856e242e89024ca5a1c4e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18791
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 4aa7ec9f78..445dcb67c1 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -157,6 +157,11 @@ struct soc_intel_skylake_config { /* Trace Hub function */ u8 EnableTraceHub; + u32 TraceHubMemReg0Size; + u32 TraceHubMemReg1Size; + + /* DCI Enable/Disable */ + u8 PchDciEn; /* Pcie Root Ports */ u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; |