From 63755128961089deba77413dad1f4f6d349a68f5 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 6 Feb 2017 21:48:48 +0530 Subject: soc/intel/skylake: Add configs for enabling DCI and TraceHub Add configs for enabling Intel TraceHub and DCI for aid in debugging. Change-Id: Ic40f9499c0125070049856e242e89024ca5a1c4e Signed-off-by: Aamir Bohra Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/18791 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/chip.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel/skylake/chip.h') diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 4aa7ec9f78..445dcb67c1 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -157,6 +157,11 @@ struct soc_intel_skylake_config { /* Trace Hub function */ u8 EnableTraceHub; + u32 TraceHubMemReg0Size; + u32 TraceHubMemReg1Size; + + /* DCI Enable/Disable */ + u8 PchDciEn; /* Pcie Root Ports */ u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; -- cgit v1.2.3