diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-07-24 15:37:13 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-13 16:33:23 +0200 |
| commit | edf1cb78e29edd768ef9641093bb3eae3c8c91d7 (patch) | |
| tree | 88b958c35863fe243504820d31f152af948a80ee /src/soc/intel/skylake/chip.h | |
| parent | 4f7cf3a4466df8f84ef352d2d496a2e7a075ac13 (diff) | |
skylake: Add Deep Sx configuration for wake pins
Add support for enabling various pins in Deep Sx by setting
a register in the mainboard devicetree.
BUG=chrome-os-partner:43079
BRANCH=none
TEST=build and boot on glados
Original-Change-Id: I1b4fb51f72b88bdc49096268bdd781750dcd089d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288920
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7555a92fecc6e78b579ec0bc18da202cb0c824e2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11170
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index d397c4e488..c04e9f80d9 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -21,6 +21,7 @@ #include <stdint.h> #include <soc/pci_devs.h> +#include <soc/pmc.h> #include <soc/serialio.h> #ifndef _SOC_CHIP_H_ @@ -112,6 +113,14 @@ struct soc_intel_skylake_config { int deep_s3_enable; int deep_s5_enable; + /* + * Deep Sx Configuration + * DSX_EN_WAKE_PIN - Enable WAKE# pin + * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin + * DSX_EN_AC_PRESENT_PIN - Enable AC_PRESENT pin + */ + uint32_t deep_sx_config; + /* TCC activation offset */ int tcc_offset; |