From edf1cb78e29edd768ef9641093bb3eae3c8c91d7 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 24 Jul 2015 15:37:13 -0700 Subject: skylake: Add Deep Sx configuration for wake pins Add support for enabling various pins in Deep Sx by setting a register in the mainboard devicetree. BUG=chrome-os-partner:43079 BRANCH=none TEST=build and boot on glados Original-Change-Id: I1b4fb51f72b88bdc49096268bdd781750dcd089d Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/288920 Original-Reviewed-by: Aaron Durbin Change-Id: I7555a92fecc6e78b579ec0bc18da202cb0c824e2 Signed-off-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/11170 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/skylake/chip.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc/intel/skylake/chip.h') diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index d397c4e488..c04e9f80d9 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -21,6 +21,7 @@ #include #include +#include #include #ifndef _SOC_CHIP_H_ @@ -112,6 +113,14 @@ struct soc_intel_skylake_config { int deep_s3_enable; int deep_s5_enable; + /* + * Deep Sx Configuration + * DSX_EN_WAKE_PIN - Enable WAKE# pin + * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin + * DSX_EN_AC_PRESENT_PIN - Enable AC_PRESENT pin + */ + uint32_t deep_sx_config; + /* TCC activation offset */ int tcc_offset; -- cgit v1.2.3