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authorAngel Pons <th3fanbus@gmail.com>2019-08-30 20:05:33 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-11-27 13:45:49 +0000
commit4ff63d3a11014fa1a54c82a3023182059c5812f1 (patch)
treece2075a44885403f46266950a6e8998db7db6bd0 /src/soc/intel/skylake/chip.c
parent941796a50d1ed3cefd503aa28b97be14e22273bb (diff)
soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot
Do it in coreboot code instead of letting FSP do it. Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/skylake/chip.c')
-rw-r--r--src/soc/intel/skylake/chip.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 1e0803c67b..de11a9e1c7 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -391,17 +391,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Set TccActivationOffset */
tconfig->TccActivationOffset = config->tcc_offset;
+ /* Already handled in coreboot code, so tell FSP to ignore UPDs */
+ params->PchIoApicBdfValid = 0;
+
/* Enable VT-d and X2APIC */
if (!config->ignore_vtd && soc_is_vtd_capable()) {
params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS;
params->X2ApicOptOut = 0;
tconfig->VtdDisable = 0;
-
- params->PchIoApicBdfValid = 1;
- params->PchIoApicBusNumber = V_P2SB_IBDF_BUS;
- params->PchIoApicDeviceNumber = V_P2SB_IBDF_DEV;
- params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN;
}
dev = pcidev_path_on_root(SA_DEVFN_IGD);