From 4ff63d3a11014fa1a54c82a3023182059c5812f1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Aug 2019 20:05:33 +0200 Subject: soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do it in coreboot code instead of letting FSP do it. Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/35170 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber --- src/soc/intel/skylake/chip.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'src/soc/intel/skylake/chip.c') diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 1e0803c67b..de11a9e1c7 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -391,17 +391,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Set TccActivationOffset */ tconfig->TccActivationOffset = config->tcc_offset; + /* Already handled in coreboot code, so tell FSP to ignore UPDs */ + params->PchIoApicBdfValid = 0; + /* Enable VT-d and X2APIC */ if (!config->ignore_vtd && soc_is_vtd_capable()) { params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; params->X2ApicOptOut = 0; tconfig->VtdDisable = 0; - - params->PchIoApicBdfValid = 1; - params->PchIoApicBusNumber = V_P2SB_IBDF_BUS; - params->PchIoApicDeviceNumber = V_P2SB_IBDF_DEV; - params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN; } dev = pcidev_path_on_root(SA_DEVFN_IGD); -- cgit v1.2.3