diff options
| author | Usha P <usha.p@intel.com> | 2019-12-23 13:21:36 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-26 10:44:00 +0000 |
| commit | 5395123b849da143d9621b67a6837defe9501acf (patch) | |
| tree | 33850e558e35eb4443aadd46bd22dec062412112 /src/soc/intel/skylake/bootblock | |
| parent | f96c638a60fdca149a716e773749c20bd4080ee3 (diff) | |
soc/intel/skylake: Rename pch_init() code
This patch renames pch_init function to bootblock_pch_init and
romstage_pch_init according to the stage it is defined in.
TEST=Able to build and boot soraka successfully.
Change-Id: Idf7b04edc3fce147f7957561ce7d5a0cd05f53fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
| -rw-r--r-- | src/soc/intel/skylake/bootblock/bootblock.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index d1fbb83b8a..26454e4b09 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -44,6 +44,6 @@ void bootblock_soc_init(void) * and abase, i2c programming and print platform info */ report_platform_info(); - pch_init(); + bootblock_pch_init(); gspi_early_bar_init(); } diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 332060ed2d..ddf1139aa0 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -146,7 +146,7 @@ void pch_early_iorange_init(void) pch_enable_lpc(); } -void pch_init(void) +void bootblock_pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, |