diff options
author | Aamir Bohra <aamir.bohra@intel.com> | 2017-04-06 11:15:18 +0530 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-04-11 16:59:30 +0200 |
commit | 015c64335d13b9e213fa93127d621c574b17018e (patch) | |
tree | f2f5e930f3e80b378b11025485cb8649d5e5586c /src/soc/intel/skylake/bootblock/uart.c | |
parent | ccfea16cd41cf2d76cb608e56ba3b81bb60156e4 (diff) |
soc/intel/skylake: Use LPSS common library
Use lpss common library to program reset and
clock register for lpss modules.
Change-Id: I198feba7c6f6d033ab77ed25a5bd9ea99411a1e4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19153
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/bootblock/uart.c')
-rw-r--r-- | src/soc/intel/skylake/bootblock/uart.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c index d51d179577..cf06359eae 100644 --- a/src/soc/intel/skylake/bootblock/uart.c +++ b/src/soc/intel/skylake/bootblock/uart.c @@ -18,12 +18,12 @@ #include <arch/io.h> #include <console/uart.h> #include <device/pci_def.h> +#include <intelblocks/lpss.h> #include <intelblocks/pcr.h> #include <stdint.h> #include <soc/bootblock.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -#include <soc/serialio.h> #include <gpio.h> /* Serial IO UART controller legacy mode */ @@ -32,6 +32,10 @@ #define PCR_SIO_PCH_LEGACY_UART1 (1 << 1) #define PCR_SIO_PCH_LEGACY_UART2 (1 << 2) +/* Clock divider parameters for 115200 baud rate */ +#define CLOCK_DIV_M_VAL 0x30 +#define CLOCK_DIV_N_VAL 0xc35 + /* UART2 pad configuration. Support RXD and TXD for now. */ static const struct pad_config uart2_pads[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), @@ -42,7 +46,7 @@ void pch_uart_init(void) { device_t dev = PCH_DEV_UART2; u32 tmp; - u8 *base = (void *)uart_platform_base(CONFIG_UART_FOR_CONSOLE); + uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); /* Set configured UART2 base address */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base); @@ -53,21 +57,14 @@ void pch_uart_init(void) pci_write_config32(dev, PCI_COMMAND, tmp); /* Take UART2 out of reset */ - tmp = read32(base + SIO_REG_PPR_RESETS); - tmp |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | - SIO_REG_PPR_RESETS_IDMA; - write32(base + SIO_REG_PPR_RESETS, tmp); + lpss_reset_release(base); /* * Set M and N divisor inputs and enable clock. * Main reference frequency to UART is: * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz */ - tmp = read32(base + SIO_REG_PPR_CLOCK); - tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE | - (SIO_REG_PPR_CLOCK_N_DIV << 16) | - (SIO_REG_PPR_CLOCK_M_DIV << 1); - write32(base + SIO_REG_PPR_CLOCK, tmp); + lpss_clk_update(base, CLOCK_DIV_M_VAL, CLOCK_DIV_N_VAL); /* Put UART2 in byte access mode for 16550 compatibility */ if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) |