soc/intel/skylake: Add C entry bootblock support

List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34

Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 4 insertions, 62 deletions

diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index d713974358..8c1e58a65f 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -15,14 +15,11 @@
  */
 
 #include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <device/pci_def.h>
+#include <delay.h>
 #include <arch/io.h>
 #include <cpu/intel/microcode/microcode.c>
 #include <reset.h>
+#include <soc/bootblock.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -33,45 +30,6 @@
 /* Soft Reset Data Register Bit 6-11 = Flex Ratio */
 #define FLEX_RATIO_BIT	6
 
-static void set_var_mtrr(
-	unsigned reg, unsigned base, unsigned size, unsigned type)
-
-{
-	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
-	msr_t basem, maskm;
-	basem.lo = base | type;
-	basem.hi = 0;
-	wrmsr(MTRR_PHYS_BASE(reg), basem);
-	maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
-	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
-	wrmsr(MTRR_PHYS_MASK(reg), maskm);
-}
-
-static void enable_rom_caching(void)
-{
-	msr_t msr;
-
-	disable_cache();
-	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
-	enable_cache();
-
-	/* Enable Variable MTRRs */
-	msr.hi = 0x00000000;
-	msr.lo = 0x00000800;
-	wrmsr(MTRR_DEF_TYPE_MSR, msr);
-}
-
-static void bootblock_mdelay(int ms)
-{
-	u32 target = ms * 24 * 1000;
-	msr_t current;
-	msr_t start = rdmsr(MSR_COUNTER_24_MHZ);
-
-	do {
-		current = rdmsr(MSR_COUNTER_24_MHZ);
-	} while ((current.lo - start.lo) < target);
-}
-
 static void set_pch_cpu_strap(u8 flex_ratio)
 {
 	uint8_t *spibar = (void *)SPI_BASE_ADDRESS;
@@ -135,31 +93,15 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	set_pch_cpu_strap(nominal_ratio);
 
 	/* Delay before reset to avoid potential TPM lockout */
-	bootblock_mdelay(30);
+	mdelay(30);
 
 	/* Issue soft reset, will be "CPU only" due to soft reset data */
 	soft_reset();
 }
 
-static void check_for_clean_reset(void)
-{
-	msr_t msr;
-	msr = rdmsr(MTRR_DEF_TYPE_MSR);
-
-	/*
-	 * Use the MTRR default type MSR as a proxy for detecting INIT#.
-	 * Reset the system if any known bits are set in that MSR. That is
-	 * an indication of the CPU not being properly reset.
-	 */
-	if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN))
-		soft_reset();
-}
-
-static void bootblock_cpu_init(void)
+void bootblock_cpu_init(void)
 {
 	/* Set flex ratio and reset if needed */
 	set_flex_ratio_to_tdp_nominal();
-	check_for_clean_reset();
-	enable_rom_caching();
 	intel_update_microcode_from_cbfs();
 }