diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-05 10:36:45 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-08 09:46:16 +0000 |
| commit | 88607a4b1002ed6acc7f316f274feea2fd861095 (patch) | |
| tree | e004c85f36109da78872b88875d4f0ea1c30aaff /src/soc/intel/skylake/acpi/xhci.asl | |
| parent | d9169f826a3c19a7380a7d73c7126e52eb62e77d (diff) | |
src: Use tabs for indentation
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/acpi/xhci.asl')
| -rw-r--r-- | src/soc/intel/skylake/acpi/xhci.asl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 29367de6dd..a23d78abd9 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -195,8 +195,8 @@ Device (XHCI) Store (3, ^UPSW) /* Enable d3hot and SS link trunk clock gating */ - Store(One, ^D3HE) - Store(One, ^STGE) + Store(One, ^D3HE) + Store(One, ^STGE) /* Now put device in D3 */ Store (3, Local0) |