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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-03-20 11:19:50 +0100 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-03-22 09:55:24 +0000 |
| commit | a5abcf2be35fcb38df47e5f74d6dcb4a3f811c6b (patch) | |
| tree | 896861988fe47f143960f6ba1f5e442f1f2c768f /src/soc/intel/skylake/acpi/pch_hda.asl | |
| parent | 84a4c762948f43615458924098f9ad50b877c8d0 (diff) | |
soc/intel/elkhartlake: Increase BSP stack size by 1 KiB to 193 KiB
The Kconfig help section says FSP uses 192 KiB of stack (0x30000) and
coreboot's romstage requires ~1 KiB, but it is not satisfied currently.
Increase the BSP stack size by the missing 1KiB for romstage like
other SoCs do.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iddd4a4613bc174aec4331732371a27450225258c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73820
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/skylake/acpi/pch_hda.asl')
0 files changed, 0 insertions, 0 deletions