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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-22 21:31:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-04 16:20:28 +0000 |
| commit | 6a8cde4927bd6bff60a783c72356fcce801511b8 (patch) | |
| tree | 44419403a33e4c21a7b907829d8ea35e9e9c497a /src/soc/intel/skylake/acpi/ipu.asl | |
| parent | eb6887e1b62513e02d2b65c783242d411e8b509c (diff) | |
soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE
The cache as ram code will use one form of a non-eviction mode.
Change-Id: I418eb48434aa3da3bf5ca65315bb8c9077523966
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/acpi/ipu.asl')
0 files changed, 0 insertions, 0 deletions