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| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2024-04-17 10:53:29 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2024-10-28 03:36:39 +0000 |
| commit | d1f9d73efc7cf6dda522c8eb984a95335883a7da (patch) | |
| tree | edeae2f6075acdc2ba2cd188ab64872b3e063ec5 /src/soc/intel/skylake/acpi/dptf/thermal.asl | |
| parent | 61e3815a255f73db2e5cc669c737fb89756a0bdb (diff) | |
mb/google/rauru: Add PCIe domain support
Add PCIe domain support.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I3e06dfaf79924cd5352348afaa526fc7dedbb540
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84700
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/acpi/dptf/thermal.asl')
0 files changed, 0 insertions, 0 deletions