diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-03-08 17:59:40 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-04-10 20:04:01 +0200 |
| commit | e7ceae79502705a8dc86943e6296fd2cf7735677 (patch) | |
| tree | 932994dc8b8a10f2a2fae49946418bd11c44dfb0 /src/soc/intel/skylake/Makefile.inc | |
| parent | d579199f968c88bdbb7e907f6e683d829215eeac (diff) | |
soc/intel/skylake: Use common PCR module
This patch use common PCR library to perform CRRd and CRWr operation
using Port Ids, define inside soc/pcr_ids.h
Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18674
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index cb8eb89514..2ef4bba143 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -22,7 +22,6 @@ bootblock-y += gpio.c bootblock-y += gspi.c bootblock-y += monotonic_timer.c bootblock-y += pch.c -bootblock-y += pcr.c bootblock-y += pmutil.c bootblock-y += spi.c bootblock-y += tsc_freq.c @@ -45,7 +44,6 @@ romstage-y += memmap.c romstage-y += monotonic_timer.c romstage-y += me.c romstage-y += pch.c -romstage-y += pcr.c romstage-y += pei_data.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c @@ -76,7 +74,6 @@ ramstage-y += monotonic_timer.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c ramstage-y += pch.c ramstage-y += pcie.c -ramstage-y += pcr.c ramstage-y += pei_data.c ramstage-y += pmc.c ramstage-y += pmutil.c @@ -98,7 +95,6 @@ ramstage-y += vr_config.c smm-y += cpu_info.c smm-y += gpio.c smm-y += monotonic_timer.c -smm-y += pcr.c smm-y += pch.c smm-y += pmutil.c smm-y += smihandler.c |