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authorKarthikeyan Ramasubramanian <kramasub@chromium.org>2019-07-03 13:02:37 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-07-19 17:13:50 +0000
commit0f718312f1b57ec300b7486c95e53562be5a2325 (patch)
treea9a224c621433a8e6af62c4d31f73011d263c145 /src/soc/intel/skylake/Makefile.inc
parenta260215a644f0f13b60c08b1a9d55d3567a380b1 (diff)
soc/intel/common: Add SOC specific function to get XHCI USB info
It feels appropriate to define SoC specific XHCI USB info in SoC specific XHCI source file and an API to get that information instead of defining it in elog source file. This will help in other situations where the information is required. BUG=None BRANCH=None TEST=Boot to ChromeOS. Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/Makefile.inc')
-rw-r--r--src/soc/intel/skylake/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 20fba29116..913a9d9b5d 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -67,6 +67,7 @@ ramstage-y += systemagent.c
ramstage-y += thermal.c
ramstage-y += uart.c
ramstage-y += vr_config.c
+ramstage-y += xhci.c
smm-y += elog.c
smm-y += gpio.c
@@ -74,6 +75,7 @@ smm-y += p2sb.c
smm-y += pmutil.c
smm-y += smihandler.c
smm-y += uart.c
+smm-y += xhci.c
postcar-y += memmap.c
postcar-y += gspi.c