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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-05-03 15:53:33 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-05-17 21:38:17 +0200 |
| commit | 4bab6e79b078c76d0a42883c4b4c9c68615d5a1e (patch) | |
| tree | 2c7dda58587f464fa1baee712c95bb48c924ff76 /src/soc/intel/sch/port_access.c | |
| parent | 083da160af4a0e3a76506af59477f105d78b9683 (diff) | |
intel/sch: Merge northbridge and southbridge in src/soc
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Diffstat (limited to 'src/soc/intel/sch/port_access.c')
| -rw-r--r-- | src/soc/intel/sch/port_access.c | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/src/soc/intel/sch/port_access.c b/src/soc/intel/sch/port_access.c new file mode 100644 index 0000000000..320c537069 --- /dev/null +++ b/src/soc/intel/sch/port_access.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009-2010 iWave Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include "sch.h" + +/* + * Restricted Access Regions: + * + * MCR - Message Control Register + * 31 24 16 8 4 0 + * ---------------------------------------------------------------------------- + * | | | Target | Write | | + * | Opcode | Port | register | byte | Reserved | + * | | | Address | Enables | | + * ---------------------------------------------------------------------------- + * + * MDR - Message Data Register + * 31 0 + * ---------------------------------------------------------------------------- + * | | + * | Data | + * | | + * ---------------------------------------------------------------------------- + */ + +#define MSG_OPCODE_READ 0xD0000000 +#define MSG_OPCODE_WRITE 0xE0000000 + +#define MCR 0xD0 +#define MDR 0xD4 + +int sch_port_access_read(int port, int reg, int bytes) +{ + pci_write_config32(PCI_DEV(0, 0, 0), MCR, + (MSG_OPCODE_READ | (port << 16) | (reg << 8))); + return pci_read_config32(PCI_DEV(0, 0, 0), MDR); +} + +void sch_port_access_write(int port, int reg, int bytes, long data) +{ + pci_write_config32(PCI_DEV(0, 0, 0), MDR, data); + pci_write_config32(PCI_DEV(0, 0, 0), MCR, + (MSG_OPCODE_WRITE | (port << 16) | (reg << 8))); + pci_read_config32(PCI_DEV(0, 0, 0), MDR); +} + +void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data) +{ + pci_write_config32(PCI_DEV(0, 0, 0), MDR, data); + pci_write_config32(PCI_DEV(0, 0, 0), MCR, + ((cmd << 24) | (port << 16) | (reg << 8))); + pci_read_config32(PCI_DEV(0, 0, 0), MDR); +} |