diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-06 07:35:11 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-21 17:37:32 +0000 |
| commit | be291e8abf173e4f12e6d9e5532fdf1acbcb9a67 (patch) | |
| tree | 12b2a0c6bcf03649b81ef38aa033b5bc06f4a7c0 /src/soc/intel/quark | |
| parent | f91344cd07a4e9a4c2e183f00431b4fee05daf33 (diff) | |
soc/intel/fsp1.1: Implement postcar stage
This moves FSP1.1 to use postcar stage to tear down CAR.
On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found
during the postcar stage so there is no need to push to save it
in CAR global variables.
On FSP1.1 platforms with an open source CAR implementation (Skylake,
even though it still runs the FSP-T), the
soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR.
This also uses common functions to set up the MTRR to use after
CAR is torn down.
Test: build/boot on google/celes (BSW) and google/chell (SKL)
Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/soc/intel/quark')
| -rw-r--r-- | src/soc/intel/quark/include/soc/romstage.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/quark/romstage/car_stage_entry.S | 6 | ||||
| -rw-r--r-- | src/soc/intel/quark/romstage/fsp2_0.c | 3 |
3 files changed, 2 insertions, 9 deletions
diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index fb8a844815..c7de080146 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -25,7 +25,7 @@ #include <soc/car.h> #include <soc/reg_access.h> -asmlinkage void *car_stage_c_entry(void); +asmlinkage void car_stage_c_entry(void); void clear_smi_and_wake_events(void); void disable_rom_shadow(void); void *locate_rmu_file(size_t *rmu_file_len); diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index d51587143b..c9847eaac7 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -29,12 +29,6 @@ car_stage_entry: /* Enter the C code */ call car_stage_c_entry -#if CONFIG(PLATFORM_USES_FSP1_1) -#if !ENV_VERSTAGE -#include "src/drivers/intel/fsp1_1/after_raminit.S" -#endif -#endif - /* The code should never reach this point */ movb $0x69, %ah jmp .Lhlt diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 31e130a398..2ec16c9f34 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -26,7 +26,7 @@ #include <soc/reg_access.h> #include <soc/storage_test.h> -asmlinkage void *car_stage_c_entry(void) +asmlinkage void car_stage_c_entry(void) { struct postcar_frame pcf; bool s3wake; @@ -83,7 +83,6 @@ asmlinkage void *car_stage_c_entry(void) postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH); run_postcar_phase(&pcf); - return NULL; } static struct chipset_power_state power_state CAR_GLOBAL; |