soc,mb/intel: clean up remaining FSP2.0 socs/boards

Remove CONFIG_...FSP2.0 based if-switches from FSP2.0-only socs/boards

Change-Id: Iae92dc2e2328b14c78ac686aaf326bd68430933b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36279
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 7 insertions, 11 deletions

diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 4ed0377a7b..b752784d15 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS
 	select C_ENVIRONMENT_BOOTBLOCK
 	select NO_MMCONF_SUPPORT
 	select REG_SCRIPT
+	select PLATFORM_USES_FSP2_0
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_RESET
 	select SOC_SETS_MSRS
@@ -113,8 +114,7 @@ config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY
 	select ENABLE_DEBUG_LED
 	help
 	  Indicate that bootblock_c_entry was entered.  If the SD LED does not
-	  light then debug the code between ESRAM and bootblock_c_entry.  For
-	  FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code.
+	  light then debug the code between ESRAM and bootblock_c_entry.
 
 config ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY
 	bool "SD LED indicates bootblock_soc_early_init successfully entered"
@@ -192,12 +192,10 @@ config FSP_ESRAM_LOC
 
 config FSP_M_FILE
 	string
-	depends on PLATFORM_USES_FSP2_0
 	default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd"
 
 config FSP_S_FILE
 	string
-	depends on PLATFORM_USES_FSP2_0
 	default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd"
 
 #####
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index f1382f5efa..cff089149d 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -37,9 +37,9 @@ romstage-y += reg_access.c
 romstage-$(CONFIG_STORAGE_TEST) += storage_test.c
 romstage-y += tsc_freq.c
 romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
-romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
+romstage-y += reset.c
 
-postcar-y += fsp2_0.c
+postcar-y += fsp_params.c
 postcar-y += i2c.c
 postcar-y += memmap.c
 postcar-y += reg_access.c
@@ -49,14 +49,14 @@ postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += chip.c
 ramstage-y += ehci.c
-ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c
+ramstage-y += fsp_params.c
 ramstage-y += gpio_i2c.c
 ramstage-y += i2c.c
 ramstage-y += lpc.c
 ramstage-y += memmap.c
 ramstage-y += northcluster.c
 ramstage-y += reg_access.c
-ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
+ramstage-y += reset.c
 ramstage-y += sd.c
 ramstage-y += spi.c
 ramstage-y += spi_debug.c
diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp_params.c
index d96d410f9a..d96d410f9a 100644
--- a/src/soc/intel/quark/fsp2_0.c
+++ b/src/soc/intel/quark/fsp_params.c
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index 13963d4b23..d90a3af5d4 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -14,10 +14,8 @@
 #
 
 romstage-y += car.c
-ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
 romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c
-romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c
-endif # CONFIG_PLATFORM_USES_FSP2_0
+romstage-y += fsp_params.c
 romstage-y += mtrr.c
 romstage-y += pcie.c
 romstage-y += report_platform.c
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp_params.c
index cd654d74de..cd654d74de 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp_params.c