diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-01-21 22:37:21 -0800 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-01-31 05:56:54 +0000 |
| commit | e2a7bf16f02de88d555c7f97189e32c45b9ae1b2 (patch) | |
| tree | 34f347966ffcb2c9a1947c9aa1d45be5a83efff3 /src/soc/intel/quark/storage_test.c | |
| parent | b2e1109f0f8dffb708041248845892e2c864a852 (diff) | |
intel/fsp: Update cannonlake fsp header
Update Cannonlake FSP header to revision 7.x.20.52. Following changes
had been made:
1. Hide internal EV related options.
2. Add GT voltage override options.
3. Add PEG IMR selection.
4. Add PCH DMI ASPM options.
TEST=NONE
Change-Id: If186a1eb440266f1eaeb03505fe0ff4c6a521be6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/quark/storage_test.c')
0 files changed, 0 insertions, 0 deletions