soc/intel/quark: Initialize some of the FADT base registers

Initialize the base addresses for:
*  Power management control
*  Power management status
*  Reset
*  Power management timer
*  General-Purpose Event 0

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
*  Edit .config file and add the following lines:
   * CONFIG_PAYLOAD_ELF=y
   * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
*  Testing successful when:
   *  Register address are properly displayed by the payload
   *  "reset -c" performs a reset and reboots the system
   *  "reset -w" performs a reset and reboots the system
   *  "reset -s" performs a reset and turns off the power

Change-Id: I9d043f4906a067b2477650140210cfae4a7f8b79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13764
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 51 insertions, 0 deletions

diff --git a/src/soc/intel/quark/pmc.c b/src/soc/intel/quark/pmc.c
new file mode 100644
index 0000000000..fbed93582e
--- /dev/null
+++ b/src/soc/intel/quark/pmc.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/ramstage.h>
+
+static void pmc_read_resources(device_t dev)
+{
+	unsigned index = 0;
+	struct resource *res;
+
+	/* Get the normal PCI resources of this device. */
+	pci_dev_read_resources(dev);
+
+	/* PMBASE */
+	res = new_resource(dev, index++);
+	res->base = ACPI_BASE_ADDRESS;
+	res->size = ACPI_BASE_SIZE;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static struct device_operations device_ops = {
+	.read_resources		= &pmc_read_resources,
+	.set_resources		= &pci_dev_set_resources,
+	.enable_resources	= &pci_dev_enable_resources,
+	.scan_bus		= &scan_lpc_bus,
+};
+
+static const struct pci_driver pmc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= QUARK_V_LPC_DEVICE_ID_0,
+};