diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-25 10:14:07 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-05 01:53:49 +0200 |
| commit | f26fc0f28bf62dd34533aea47105f174ee794e66 (patch) | |
| tree | 5bcb26ddc174f46ff7acbd5ab6689320c74f9a99 /src/soc/intel/quark/fsp2_0.c | |
| parent | 102f6253600cfa3f741c0d1d126436d612daa203 (diff) | |
soc/intel/quark: Add FSP 2.0 romstage support
Add the pieces necessary to successfully build and run romstage using
the FSP 2.0 build. Because romstage is using postcar, add the postcar
pieces so that romstage can attempt to load postcar.
TEST=Build and run on Galileo Gen2
Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15866
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/fsp2_0.c')
| -rw-r--r-- | src/soc/intel/quark/fsp2_0.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp2_0.c index dccd28ef85..deb933427d 100644 --- a/src/soc/intel/quark/fsp2_0.c +++ b/src/soc/intel/quark/fsp2_0.c @@ -19,3 +19,7 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) { } + +asmlinkage void chipset_teardown_car(void) +{ +} |