From f26fc0f28bf62dd34533aea47105f174ee794e66 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Mon, 25 Jul 2016 10:14:07 -0700 Subject: soc/intel/quark: Add FSP 2.0 romstage support Add the pieces necessary to successfully build and run romstage using the FSP 2.0 build. Because romstage is using postcar, add the postcar pieces so that romstage can attempt to load postcar. TEST=Build and run on Galileo Gen2 Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/15866 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/quark/fsp2_0.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/quark/fsp2_0.c') diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp2_0.c index dccd28ef85..deb933427d 100644 --- a/src/soc/intel/quark/fsp2_0.c +++ b/src/soc/intel/quark/fsp2_0.c @@ -19,3 +19,7 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) { } + +asmlinkage void chipset_teardown_car(void) +{ +} -- cgit v1.2.3