diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-02-02 07:17:06 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-02-08 20:15:05 +0100 |
| commit | 9fd0895cb4a8cf8d4ece09d62628b6d4b91177ae (patch) | |
| tree | 2337f3f48f7c4dce491edb04a7530e6749f83fda /src/soc/intel/quark/Kconfig | |
| parent | cff5f09e9340229cade13960f1c08ede7ec5596f (diff) | |
soc/intel/quark: Enable ESRAM
The Quark SoC uses ESRAM instead of cache-as-RAM. This code requires
that utils/xcompile/xcompile change the machine architecture from i686
to i586 to ensure that the Quark does not attempt to execute unsupported
instructions:
* Adjust Makefile.inc to add the RMU to the coreboot image
* Add code to enable the ESRAM
Directly use the QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h
file from the EDK2 tree (https://github.com/tianocore/edk2.git) to
enable
easy differences and correct issues in coreboot that were found in EDK2.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_RMU_FILE"
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Remove power from the board
* Apply power to the board
* Testing is successful if the SD LED is on indicating that the end of
esram_init.inc was reached
Change-Id: I91d919da144bb72a5d4c4a8050ffab256632a395
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13440
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark/Kconfig')
| -rw-r--r-- | src/soc/intel/quark/Kconfig | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 866b66d011..1bfab49c95 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -28,4 +28,48 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select USE_MARCH_586 +##### +# Flash layout +# Specify the size of the coreboot file system in the read-only +# (recovery) portion of the flash part. +##### + +config CBFS_SIZE + hex + default 0x200000 + help + Specify the size of the coreboot file system in the read-only (recovery) + portion of the flash part. On Quark systems the firmware image stores + more than just coreboot, including: + - The chipset microcode (RMU) binary file located at 0xFFF00000 + - Intel Trusted Execution Engine firmware + +##### +# RMU binary +# The following options control the Quark chipset microcode file +# placement in the flash image. This file is required to bring +# the Quark processor out of reset. +##### + +config ADD_RMU_FILE + bool "Should the RMU binary be added to the flash image?" + default n + help + The RMU file is required to get the chip out of reset. + +config RMU_FILE + string + default "3rdparty/blobs/soc/intel/quark/rmu.bin" + depends on ADD_RMU_FILE + help + The path and filename of the Intel Quark RMU binary. + +config RMU_LOC + hex + default 0xfff00000 + depends on ADD_RMU_FILE + help + The location in CBFS that the RMU is located. It must match the + strap-determined base address. + endif # SOC_INTEL_QUARK |