soc/intel/pantherlake: Add FSP-M programming

FSP-M UPDs are programmed according to the configuration (Kconfig and
device tree).

BUG=348678529
TEST=Memory is initialized successfully and hardware is programmed as
     desired on Intel pantherlake reference board.

Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6988
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84443
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 10 insertions, 1 deletions

diff --git a/src/soc/intel/pantherlake/include/soc/meminit.h b/src/soc/intel/pantherlake/include/soc/meminit.h
index 78c509b519..7b72f9991c 100644
--- a/src/soc/intel/pantherlake/include/soc/meminit.h
+++ b/src/soc/intel/pantherlake/include/soc/meminit.h
@@ -8,9 +8,15 @@
 #include <types.h>
 
 enum mem_type {
+	MEM_TYPE_DDR5,
 	MEM_TYPE_LP5X,
 };
 
+struct mem_ddr_config {
+	/* Dqs Pins Interleaved Setting. Enable/Disable Control */
+	bool dq_pins_interleaved;
+};
+
 struct lpx_dq {
 	uint8_t dq0[BITS_PER_BYTE];
 	uint8_t dq1[BITS_PER_BYTE];
@@ -83,7 +89,10 @@ struct mb_cfg {
 		struct lpx_dqs_map lpx_dqs_map;
 	};
 
-	struct mem_lp5x_config lp5x_config;
+	union {
+		struct mem_lp5x_config lp5x_config;
+		struct mem_ddr_config ddr_config;
+	};
 
 	/* Early Command Training Enable/Disable Control */
 	bool ect;