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authorJeremy Compostella <jeremy.compostella@intel.com>2024-09-20 12:13:11 -0700
committerSubrata Banik <subratabanik@google.com>2024-09-26 03:57:37 +0000
commit1005e49580467437cdbe2db8f0c3b6c9b81da357 (patch)
treed476c5f6dcbe55679a6de42b1c5ede0319825072 /src/soc/intel/pantherlake/bootblock
parent8619d951b3b8b4cb07d5da108421f5dc4a793642 (diff)
soc/intel/ptl: Remove tcss_d3_hot_disable en config structure field
This commit drops tcss_d3_hot_disable chip config as FSP is not exposing the same purpose UPD anymore starting with Panther Lake SoC. BUG=b:348678529 TEST=Build for fatcat Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d58 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Diffstat (limited to 'src/soc/intel/pantherlake/bootblock')
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