diff options
| author | Dinesh Gehlot <digehlot@google.com> | 2022-12-12 08:48:14 +0000 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-12-22 18:54:18 +0000 |
| commit | 36b6b055bd259a6fcc2a15afc04424c8f9434f39 (patch) | |
| tree | 1d74e574951cb1966344fe7a203da80fac95f84a /src/soc/intel/meteorlake | |
| parent | 9f47f958b3e048d78dcbec368b845578c76c8542 (diff) | |
soc/intel/meteorlake: Add ASPM setting in pcie_rp_config
This change provides config for devicetree to control ASPM per port
TEST=Build and Boot verified on google/rex
Port of 'commit 6e52c1da4a22 ("soc/intel/{adl,common}:
Add ASPM setting in pcie_rp_config)'
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I284bf51628193aa5f82f21fbf29c57a6ea5f9cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/meteorlake')
| -rw-r--r-- | src/soc/intel/meteorlake/fsp_params.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index ad6db109e4..d40779ab79 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -93,6 +93,21 @@ static int get_l1_substate_control(enum L1_substates_control ctl) return ctl - 1; } +/* + * get_aspm_control() ensures that the right UPD value is set in fsp_params. + * 0: Disable ASPM + * 1: L0s only + * 2: L1 only + * 3: L0s and L1 + * 4: Auto configuration + */ +static unsigned int get_aspm_control(enum ASPM_control ctl) +{ + if (ctl > ASPM_AUTO) + ctl = ASPM_AUTO; + return ctl; +} + __weak void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config) { /* Override settings per board. */ @@ -393,6 +408,8 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); + if (rp_cfg->pcie_rp_aspm) + s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); } s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); } |