diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2023-03-13 14:27:30 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-04-04 08:08:35 +0000 |
| commit | 34c37bb1c58f2be5933281c9bff3c033fb939d74 (patch) | |
| tree | c220499174fd38acba874f4f05093c8e11e4b681 /src/soc/intel/meteorlake | |
| parent | 28ac0fd2f094875bd81afd8cb96f08e0cf71d2c7 (diff) | |
soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table
Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table.
990:CSME ROM started execution 0
944:CSE sent 'Boot Stall Done' to PMC 47,000
945:CSE started to handle ICC configuration 225,000 (178,000)
946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0)
947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000)
991:Die Management Unit (DMU) load completed 587,000 (71,000)
0:1st timestamp 597,427 (10,427)
BUG=b:259366109
TEST=Able to see TS elapse prior to IA reset on Rex
Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73713
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Diffstat (limited to 'src/soc/intel/meteorlake')
| -rw-r--r-- | src/soc/intel/meteorlake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/cse_telemetry.c | 29 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/romstage.c | 4 |
3 files changed, 34 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/Makefile.inc b/src/soc/intel/meteorlake/Makefile.inc index 87fb3a3228..fd94cdaf81 100644 --- a/src/soc/intel/meteorlake/Makefile.inc +++ b/src/soc/intel/meteorlake/Makefile.inc @@ -21,6 +21,7 @@ bootblock-y += espi.c bootblock-y += p2sb.c bootblock-y += soc_info.c +romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c romstage-y += espi.c romstage-y += meminit.c romstage-y += pcie_rp.c diff --git a/src/soc/intel/meteorlake/cse_telemetry.c b/src/soc/intel/meteorlake/cse_telemetry.c new file mode 100644 index 0000000000..7f5d947a28 --- /dev/null +++ b/src/soc/intel/meteorlake/cse_telemetry.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <intelblocks/cse.h> +#include <timestamp.h> + +void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time) +{ + s64 start_stamp; + + if (!ts) { + printk(BIOS_ERR, "%s: Failed to insert CSME timestamps\n", __func__); + return; + } + + start_stamp = current_time - ts[PERF_DATA_CSME_GET_PERF_RESPONSE]; + + timestamp_add(TS_ME_ROM_START, start_stamp); + timestamp_add(TS_ME_BOOT_STALL_END, + start_stamp + ts[PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC]); + timestamp_add(TS_ME_ICC_CONFIG_START, + start_stamp + ts[PERF_DATA_CSME_GOT_ICC_CFG_START_MSG_FROM_PMC]); + timestamp_add(TS_ME_HOST_BOOT_PREP_END, + start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); + timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, + start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); + timestamp_add(TS_ESE_DMU_LOAD_END, + start_stamp + ts[PERF_DATA_ESE_DMU_LOAD_COMPLETED]); +} diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index 2df3e11d7a..ebb440c5f9 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -134,6 +134,10 @@ void mainboard_romstage_entry(void) timestamp_add_now(TS_CSE_FW_SYNC_END); } + /* Update coreboot timestamp table with CSE timestamps */ + if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY)) + cse_get_telemetry_data(); + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ |