diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2022-05-07 16:37:09 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-06-29 05:28:39 +0000 |
| commit | 91ffac8c04776e1e663c5987ea718522f605a9b4 (patch) | |
| tree | 255b839904b8aca2206d721f185948c7f27a4865 /src/soc/intel/meteorlake/uart.c | |
| parent | febd3d756b8ef4c6b6f8b5be9e2558d8cdd5a6ae (diff) | |
soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Fill required FSP-S UPD to call FSP-S API
BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/meteorlake/uart.c')
| -rw-r--r-- | src/soc/intel/meteorlake/uart.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/uart.c b/src/soc/intel/meteorlake/uart.c new file mode 100644 index 0000000000..9f549c5ae8 --- /dev/null +++ b/src/soc/intel/meteorlake/uart.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/helpers.h> +#include <soc/pci_devs.h> + +const unsigned int uart_devices[] = { + PCI_DEVFN_UART0, + PCI_DEVFN_UART1, + PCI_DEVFN_UART2, +}; + +const int uart_devices_size = ARRAY_SIZE(uart_devices); |