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authorSubrata Banik <subratabanik@google.com>2022-12-06 14:03:07 +0530
committerSubrata Banik <subratabanik@google.com>2022-12-10 08:01:09 +0000
commitc0f4b1258dee579070be43c13f0f9fbc1313388b (patch)
tree278b78358014316baeddf9e6301853a624f9067b /src/soc/intel/meteorlake/me.c
parent64dd9d000e369761e2da9d7b53e60c3296bd1890 (diff)
soc/intel/meteorlake: Support PCIe hardware compliance test mode
The validation process verifies that hardware components comply with the standard hardware specifications. For instance, PCI express implementation must comply with the hardware PCIe specification requirements: Electrical, Configuration, Link Protocol and Transaction Protocol. To perform these tests the hardware must be configured in a particular state: some feature related to power management need to be turned off, hot plug should be enabled... This patch sets the appropriate FSP Updateable Product Data flags to get the hardware in the proper configuration: - Enable PCIe hotplug on all ports - Set clock sources to run free - Set the FSP compliance test mode flag This patch is backported from commit 096ce1444ec7fa204f331a75c2ac9d00ea00bf12 (soc/intel/alderlake: Support PCIe hardware compliance test mode) Change-Id: Idd7a1adf0f53b014093ba70fee599dbb7887a0fc Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70416 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/meteorlake/me.c')
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