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authorFrank Chu <Frank_Chu@pegatron.corp-partner.google.com>2022-11-18 16:18:43 +0800
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2022-11-24 05:28:50 +0000
commit77c4d6165dcb0be7164b22ae57861a0d0ce7df4c (patch)
tree64579b4c86b83605680584b8428457b0c8beff33 /src/soc/intel/meteorlake/me.c
parent461f2a9ba08ce0f3c7ef97f466deaa6ac7c14e25 (diff)
mb/google/brya/var/marasov: Update SPD ID assignment
Adjust SPD ID order DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 1 (0001) MT62F1G32D4DR-031 WT:B 2 (0010) H9JCNNNCP3MLYR-N6E 3 (0011) BUG=b:254365935 BRANCH=None TEST=run part_id_gen to generate SPD id Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I3a62cf355508debce387c48d9d089e73763b2bf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69784 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/meteorlake/me.c')
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