diff options
| author | Kane Chen <kane.chen@intel.corp-partner.google.com> | 2024-04-12 21:16:15 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-05-07 12:50:37 +0000 |
| commit | 8c927c4dbf94a140a460b935f87fb1002532c6f7 (patch) | |
| tree | 7fbf7b5dbca683b31ecb78bb6dbc873b7082e28c /src/soc/intel/meteorlake/include | |
| parent | 8bcd8210ea64bdbb35485d361e645f2c9cfcf763 (diff) | |
soc/intel/mtl: Fixed TBT PCIe devtree remapping
The TBT PCIe devicetree settings are not remapped properly when
TBT PCIe port 0 is disabled.
This code refer SHA:58bc5d937 to remap the PCIe devtree settings
properly in case of TBT PCIe port0 is disabled,
TEST=Tested on screebo and found "Remapping PCIe Root Port #2 msg"
showed up in coreboot log
Change-Id: I7c7549ddf8ccdd67d7af7c69f51a84614cff9a03
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81841
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/meteorlake/include')
| -rw-r--r-- | src/soc/intel/meteorlake/include/soc/pcie.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/include/soc/pcie.h b/src/soc/intel/meteorlake/include/soc/pcie.h index f97543c916..7c098e9ca5 100644 --- a/src/soc/intel/meteorlake/include/soc/pcie.h +++ b/src/soc/intel/meteorlake/include/soc/pcie.h @@ -6,5 +6,6 @@ #include <intelblocks/pcie_rp.h> const struct pcie_rp_group *get_pcie_rp_table(void); +const struct pcie_rp_group *get_tbt_pcie_rp_table(void); #endif /* __SOC_METEORLAKE_PCIE_H__ */ |