diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-07-16 13:30:28 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-07-18 06:01:39 +0000 |
| commit | 825092a621af7b80d6289dd2d28ee03591e9e314 (patch) | |
| tree | 07ce377e559a4588587dbdbbb273b3d3764311a3 /src/soc/intel/meteorlake/include | |
| parent | 59e65e93777a2a94c984f9c5b9df43c9adcd58dc (diff) | |
soc/intel/meteorlake: Switch to common eSPI header
This patch updates Meteor Lake code to use the common eSPI header
file(`intelpch/espi.h`) instead of the SoC-specific one.
BUG=none
TEST=Builds successfully for google/rex.
Change-Id: Ibb37413bb6c925650f55b0dcf70e7483bf257888
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/soc/intel/meteorlake/include')
| -rw-r--r-- | src/soc/intel/meteorlake/include/soc/espi.h | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/src/soc/intel/meteorlake/include/soc/espi.h b/src/soc/intel/meteorlake/include/soc/espi.h deleted file mode 100644 index 0b03cbaa75..0000000000 --- a/src/soc/intel/meteorlake/include/soc/espi.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_METEORLAKE_ESPI_H_ -#define _SOC_METEORLAKE_ESPI_H_ - -/* PCI Configuration Space (D31:F0): ESPI */ -#define SCI_IRQ_SEL (7 << 0) -#define SCIS_IRQ9 0 -#define SCIS_IRQ10 1 -#define SCIS_IRQ11 2 -#define SCIS_IRQ20 4 -#define SCIS_IRQ21 5 -#define SCIS_IRQ22 6 -#define SCIS_IRQ23 7 -#define SERIRQ_CNTL 0x64 -#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ -#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1 */ -#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2 */ -#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ -#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ -#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ -#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ -#define LGMR 0x98 /* ESPI Generic Memory Range */ -#define PCCTL 0xE0 /* PCI Clock Control */ -#define CLKRUN_EN (1 << 0) - -#endif |