soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstage

List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Fill required FSP-S UPD to call FSP-S API

BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 161 insertions, 0 deletions

diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c
new file mode 100644
index 0000000000..8213143818
--- /dev/null
+++ b/src/soc/intel/meteorlake/cpu.c
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/turbo.h>
+#include <cpu/intel/common/common.h>
+#include <fsp/api.h>
+#include <intelblocks/cpulib.h>
+#include <intelblocks/mp_init.h>
+#include <intelblocks/msr.h>
+#include <intelblocks/acpi.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+#include <soc/soc_chip.h>
+#include <soc/soc_info.h>
+#include <assert.h>
+
+bool cpu_soc_is_in_untrusted_mode(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_BIOS_DONE);
+	return !!(msr.lo & ENABLE_IA_UNTRUSTED);
+}
+
+uint8_t get_supported_lpm_mask(void)
+{
+	return LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2;
+}
+
+static void soc_fsp_load(void)
+{
+	fsps_load();
+}
+
+static void configure_misc(void)
+{
+	msr_t msr;
+
+	config_t *conf = (config_t *)config_of_soc();
+
+	msr = rdmsr(IA32_MISC_ENABLE);
+	msr.lo |= (1 << 0);	/* Fast String enable */
+	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+
+	/* Set EIST status */
+	cpu_set_eist(conf->eist_enable);
+
+	/* Disable Thermal interrupts */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(IA32_THERM_INTERRUPT, msr);
+
+	/* Enable package critical interrupt only */
+	msr.lo = 1 << 4;
+	msr.hi = 0;
+	wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
+
+	/* Enable PROCHOT */
+	msr = rdmsr(MSR_POWER_CTL);
+	msr.lo |= (1 << 0);	/* Enable Bi-directional PROCHOT as an input*/
+	msr.lo |= (1 << 23);	/* Lock it */
+	wrmsr(MSR_POWER_CTL, msr);
+}
+
+enum core_type get_soc_cpu_type(void)
+{
+	if (cpu_is_hybrid_supported())
+		return cpu_get_cpu_type();
+	else
+		return CPUID_CORE_TYPE_INTEL_CORE;
+}
+
+void soc_get_scaling_factor(u16 *big_core_scal_factor, u16 *small_core_scal_factor)
+{
+	*big_core_scal_factor = 127;
+	*small_core_scal_factor = 100;
+}
+
+bool soc_is_nominal_freq_supported(void)
+{
+	return true;
+}
+
+/* All CPUs including BSP will run the following function. */
+void soc_core_init(struct device *cpu)
+{
+	/* Clear out pending MCEs */
+	/* TODO(adurbin): This should only be done on a cold boot. Also, some
+	 * of these banks are core vs package scope. For now every CPU clears
+	 * every bank. */
+	mca_configure();
+
+	enable_lapic_tpr();
+
+	/* Configure Enhanced SpeedStep and Thermal Sensors */
+	configure_misc();
+
+	enable_pm_timer_emulation();
+
+	/* Enable Direct Cache Access */
+	configure_dca_cap();
+
+	/* Set energy policy */
+	set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+	/* Enable Turbo */
+	enable_turbo();
+}
+
+static void per_cpu_smm_trigger(void)
+{
+	/* Relocate the SMM handler. */
+	smm_relocate();
+}
+
+static void post_mp_init(void)
+{
+	/* Set Max Ratio */
+	cpu_set_max_ratio();
+
+	/*
+	 * 1. Now that all APs have been relocated as well as the BSP let SMIs
+	 * start flowing.
+	 * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT
+	 * to avoid shutdown hang due to lack of init on certain IP in FSP-S.
+	 */
+	global_smi_enable_no_pwrbtn();
+}
+
+static const struct mp_ops mp_ops = {
+	/*
+	 * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
+	 * that are set prior to ramstage.
+	 * Real MTRRs programming are being done after resource allocation.
+	 */
+	.pre_mp_init = soc_fsp_load,
+	.get_cpu_count = get_cpu_count,
+	.get_smm_info = smm_info,
+	.get_microcode_info = get_microcode_info,
+	.pre_mp_smm_init = smm_initialize,
+	.per_cpu_smm_trigger = per_cpu_smm_trigger,
+	.relocation_handler = smm_relocation_handler,
+	.post_mp_init = post_mp_init,
+};
+
+void soc_init_cpus(struct bus *cpu_bus)
+{
+	if (mp_init_with_smm(cpu_bus, &mp_ops))
+		printk(BIOS_ERR, "MP initialization failure.\n");
+
+	/* Thermal throttle activation offset */
+	configure_tcc_thermal_target();
+}