diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2022-05-08 00:27:31 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-06-29 05:29:00 +0000 |
| commit | e02fd83eba7bb20956e0d1d1ef18f28f146b0340 (patch) | |
| tree | 87a53885dc721ce2c9a808202ee1598269f152a2 /src/soc/intel/meteorlake/acpi/xhci.asl | |
| parent | 91ffac8c04776e1e663c5987ea718522f605a9b4 (diff) | |
soc/intel/mtl/acpi: Add SoC ACPI directory for Meteor Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH,
LAN, HDA etc.
BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Change-Id: Iebe3d38f50e202d75add88f336b5f3e9ba9f5a22
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64168
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/meteorlake/acpi/xhci.asl')
| -rw-r--r-- | src/soc/intel/meteorlake/acpi/xhci.asl | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/acpi/xhci.asl b/src/soc/intel/meteorlake/acpi/xhci.asl new file mode 100644 index 0000000000..34b96f35d7 --- /dev/null +++ b/src/soc/intel/meteorlake/acpi/xhci.asl @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpe.h> + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Meteorlake */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + /* USB3 */ + Device (SS01) { Name (_ADR, 11) } + Device (SS02) { Name (_ADR, 12) } + } +} |