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authorSean Rhodes <sean@starlabs.systems>2023-04-19 08:48:33 +0100
committerLean Sheng Tan <sheng.tan@9elements.com>2023-06-01 19:00:03 +0000
commit21e61847c4cf643d79855deba8f58fd45808d571 (patch)
tree8288b7994347a2d9355a80ae4f2f85260a197c59 /src/soc/intel/jasperlake
parent51bb3afe9c5f04114c94dcf0bd45ee8a21bf8312 (diff)
soc/intel/jasperlake: Enable early caching of RAMTOP region
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/jasperlake')
-rw-r--r--src/soc/intel/jasperlake/Kconfig3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 660b24a79d..4ecec60104 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -73,7 +73,8 @@ config CPU_SPECIFIC_OPTIONS
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
- select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
+ select SOC_INTEL_COMMON_BASECODE
+ select SOC_INTEL_COMMON_BASECODE_RAMTOP
config DCACHE_RAM_BASE
default 0xfef00000