diff options
| author | V Sowmya <v.sowmya@intel.com> | 2020-07-24 08:58:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-08-17 05:14:05 +0000 |
| commit | 7aee5c67a11bed7ae028aac6752ed2f31868b43e (patch) | |
| tree | 259c7fa4de768fbaf1083ded3480ec1150c674ef /src/soc/intel/jasperlake/spd/lp4x/spd-6.hex | |
| parent | 43f0dcbb7700da216039909992951f8b7b64b071 (diff) | |
soc/intel/jasperlake: Add FSP UPDs for minimum assertion widths
Add the FSP UPDs for the chipset minimum assertion widths and
Power cycle duration to the chip options which can be configured
per mainboard.
* PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy
* PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy
* PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy
* PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy
* PchPmPwrCycDur: PCH PM Reset Power Cycle Duration
* Check to avoid violating the PCH EDS recommendation for the
PchPmPwrCycDur setting.
BUG=b:159104150
Change-Id: I042e8e34b7dfda3bc21e5f2e6727cb7692ffc7f7
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/jasperlake/spd/lp4x/spd-6.hex')
0 files changed, 0 insertions, 0 deletions