diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2020-07-21 19:12:53 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-08-18 13:56:27 +0000 |
| commit | d980339aca2aa63a946696211645cdd4968f4bbe (patch) | |
| tree | 2b936a253fdb4ea333cf65ea5869416a5ed718b4 /src/soc/intel/jasperlake/include | |
| parent | 6aa6f1f874c26c7d47c579d5adca0d866b8b0ee4 (diff) | |
soc/intel/jasperlake: Fix PMC_GPE_DW mapping
PMC_GPE_DW mapping was not configured correctly and hence
coreboot skipped programming Tier 1 GPIOs resulting in failure of
S3 wake from Trackpad.
TEST=System should wake from S3 via trackpad
Change-Id: I59ce3720e0ffeefb2c9440bb300689def80211ea
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/soc/intel/jasperlake/include')
| -rw-r--r-- | src/soc/intel/jasperlake/include/soc/pmc.h | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index 5954a3115d..9eaa812ce4 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -102,16 +102,17 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) -#define PMC_GPP_A 0x0 +#define PMC_GPP_G 0x0 #define PMC_GPP_B 0x1 -#define PMC_GPP_F 0x2 -#define PMC_GPD 0x3 -#define PMC_GPP_R 0x4 -#define PMC_GPP_S 0x6 +#define PMC_GPP_A 0x2 +#define PMC_GPP_R 0x3 +#define PMC_GPP_S 0x4 +#define PMC_GPD 0x5 +#define PMC_GPP_H 0x6 #define PMC_GPP_D 0x7 -#define PMC_GPP_C 0x8 -#define PMC_GPP_H 0xA -#define PMC_GPP_E 0xF +#define PMC_GPP_F 0x8 +#define PMC_GPP_C 0xA +#define PMC_GPP_E 0xB #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) |