soc/intel/jasperlake: correct IRQ routing Jasper Lake

Current Interrupt setting use 2nd parameters as device function number.
Correct as interrupt pin number according to _PRT package format.
{Address, pin, Source, Source index}

Reference:
- ACPI spec 6.2.13 _PRT

BUG=None
BRANCH=None
TEST=Build and boot JSLRVP Verify Interrupt mappings are same as PCI
INTR(0x3C) register and no interrupt storm is seen

Change-Id: I21462c6befea310a49eecf9ad1b5c8770eccd5bd
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41404
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 10 insertions, 48 deletions

diff --git a/src/soc/intel/jasperlake/include/soc/irq.h b/src/soc/intel/jasperlake/include/soc/irq.h
index beee7350b3..19033293ec 100644
--- a/src/soc/intel/jasperlake/include/soc/irq.h
+++ b/src/soc/intel/jasperlake/include/soc/irq.h
@@ -9,7 +9,7 @@
 #define PCH_IRQ10 10
 #define PCH_IRQ11 11
 
-/* LPSS Devices */
+/* LPSS Device IRQs */
 #define LPSS_I2C0_IRQ 16
 #define LPSS_I2C1_IRQ 17
 #define LPSS_I2C2_IRQ 18
@@ -23,52 +23,14 @@
 #define LPSS_UART1_IRQ 21
 #define LPSS_UART2_IRQ 34
 
-/* PCI D:31 F:x */
-#define cAVS_INTA_IRQ 16
-#define SMBUS_INTA_IRQ 16
-#define SMBUS_INTB_IRQ 17
-#define GbE_INTA_IRQ 16
-#define GbE_INTC_IRQ 18
-#define TRACE_HUB_INTA_IRQ 16
-#define TRACE_HUB_INTD_IRQ 19
-
-/* PCI D:28 F:x */
-#define PCIE_1_IRQ 16
-#define PCIE_2_IRQ 17
-#define PCIE_3_IRQ 18
-#define PCIE_4_IRQ 19
-#define PCIE_5_IRQ 16
-#define PCIE_6_IRQ 17
-#define PCIE_7_IRQ 18
-#define PCIE_8_IRQ 19
-
-/* PCI D:26 F:x */
-#define eMMC_IRQ 16
-
-/* PCI D:23 F:x */
-#define SATA_IRQ 16
-
-/* PCI D:22 F:x */
-#define HECI_1_IRQ 16
-#define HECI_2_IRQ 17
-#define HECI_3_IRQ 16
-#define HECI_4_IRQ 19
-#define IDER_IRQ 18
-#define KT_IRQ 19
-
-/* PCI D:20 F:x */
-#define XHCI_IRQ 16
-#define OTG_IRQ 17
-#define CNViWIFI_IRQ 16
-#define SD_IRQ 19
-#define PMC_SRAM_IRQ 18
-
-/* PCI D:18 F:x */
-#define UFS_IRQ 16
-
-#define IGFX_IRQ 16
-#define SA_THERMAL_IRQ 16
-#define IPU_IRQ 16
-#define GNA_IRQ 16
+/* PCI shared IRQs */
+#define PCH_IRQ_16 16
+#define PCH_IRQ_17 17
+#define PCH_IRQ_18 18
+#define PCH_IRQ_19 19
+#define PCH_IRQ_20 20
+#define PCH_IRQ_21 21
+#define PCH_IRQ_22 22
+#define PCH_IRQ_23 23
 
 #endif /* _JSL_IRQ_H_ */