diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-11-18 15:07:33 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-26 23:39:16 +0000 |
| commit | 9018dee6856791ab599463a771826936c20a80bb (patch) | |
| tree | 079e966e6b894bb9c81ca25e9e783c28947e0e64 /src/soc/intel/jasperlake/fsp_params.c | |
| parent | 5aa98964fb4e2e8c10b1663f8d6a3faa2b700410 (diff) | |
src/soc/intel: Remove unnecessary space after casts
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/jasperlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/jasperlake/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index a5bcd55c8f..09be260111 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -67,7 +67,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Use coreboot MP PPI services if Kconfig is enabled */ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); /* Chipset Lockdown */ const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; |